The present invention relates to a method for manufacturing semiconductor devices, and more particularly it relates to a manufacturing method especially suitable for manufacturing very high frequency semiconductor devices.
Among the conventional methods for forming a pattern of polycrystalline silicon (hereinafter polysilicon) onto a semiconductor device, a method is known in which: a layer of polysilicon is formed on a device; a photoresist layer is formed on the polysilicon layer; and the polysilicon layer is selectively etched by using a mask of resist pattern formed by photolithography.
The above method has been used in manufacturing semiconductor devices comprising bipolar transistors or metal oxide semiconductor (MOS) transistors. The method known in the art, however, has the various problems mentioned hereunder, and therefore, it has not been suitable for manufacture of very large scaled integrated circuits (VLSI) or high frequency transistors particularly requiring an extra miniaturized structure.
That is, with this method, although the polysilicon layer is etched by using a mask of resist pattern, the resist itself is also corroded during etching the polysilicon layer. Therefore, the polysilicon layer can not be etched to have a definite width pattern as intended, and in many cases, the polysilicon layer has been excessively side-etched. In particular, when the polysilicon layer contains impurities such as phosphorus or arsenic at a high concentration level, an intimate contact between the polysilicon layer and the resist becomes worse. As a result, by patterning the polysilicon layer containing high concentrated impurities by using a mask of the resist pattern described above, the resultant polysilicon pattern is extremely thinned as from the predetermined dimension.
Thus, if the manufacture process of semiconductor devices includes an etching process for polysilicon, the configuration and dimension of the pattern of polysilicon after subjected to etching becomes to a large extent different from the dimensions and configuration of the designed mask, resulting in degrading the performance of semiconductor devices. For example, when doped polysilicon is used as a resistance or capacitance, the value of resistance or capacitance can not be controlled exactly because of the fact that the polysilicon can not be precisely etched.
Further, in the manufacture of devices, such as high frequency bipolar transistors, field effect transistors (FETs), or bipolar LSI and MOS LSI semiconductors, which require very fine miniaturized structures, if the etching dimension for the polysilicon is determined to have some margins or allowances in designing the mask, the degradation of device performance becomes of more increasing importance than the lowering of a yield. For example, in the manufacture of a very high frequency npn bipolar type silicon planar transistor, and in the formation of an electrode metal pattern on an arsenic (or phosphorus) doped polysilicon which is used as a diffusion source for an emitter, it is here assumed that the etching dimension is determined to have some margins in order to prevent exposure of an emitter diffusion window of an insulation layer due to a "thinning" caused during etching the polysilicon. Then, the distance between the edge of the polysilicon pattern and the base region increases, and the distance between the edges of the emitter region and the base region increases as well, so that the high frequency performance of the transistor is deteriorated.
In addition, in the case when an electrode metal pattern is formed on the doped polysilicon pattern with an extraordinary miniaturized structure, according to the conventional method since the doped polysilicon pattern and electrode metal pattern can not be formed at the same time with the same patterning process, a shear in alignment of both patterns comes into existence. As a result, for example, in the case of a very high frequency transistor, there causes a poor contact due to the shear between the polysilicon on the emitter and the base electrode. It has been impossible to narrow the distance between the edges of emitter and base regions more than a certain distance required for preventing such a poor contact. Therefore, with the conventional method, it has been impossible to improve the performance of a very high frequency transistor, and also to implement VLSI in a higher integration density.
Apart from the first method described above, in order to manufacture VLSI transistors or high frequency transistors, a second method is also known in the art which forms n.sup.+ and p.sup.+ regions in a silicon semiconductor body with a self-alignment technique (or without using a mask). In the second method, a resist pattern is formed which exposes opening portions of two openings provided on an oxide layer, donor and acceptor impurities are ion implanted into a silicon semiconductor substrate through the respective opening portions by using the resist pattern and oxide layer as a mask, and thereafter the substrate is subjected to annealing to form semiconductor regions opposite conductivity from each other in the substrate.
With the second method, however, though it is possible to design the dimension of a mask with some margins considering the side etching effect, the design with some margins makes the dimension of a single pellet large, thereby reducing the number of pellets obtainable from a single wafer and resulting in a low yield.
Further, with the second method, there have been brought about some problems including: (1) a channelling is liable to occur since the ion implantation is carried out directly into the silicon semiconductor substrate, (2) a device defect may easily appear on the surface of the silicon semiconductor substrate, and (3) in order to make the surface portion of the silicon semiconductor substrate at a high dopant concentration, the ion acceleration voltage must be lowered considerably. However, an ion implantation apparatus presently available has in effect a limit in the acceleration voltage so that it is difficult to make only the surface portion of the substrate at a high doping level.
Further in addition, when the second method is compared with, for example, a case in which ion doped polysilicon is employed as an emitter diffusion source and electrode, some other problems inappropriate for high frequency devices are found in that an emitter diffusion efficiency is worsened in proportion to an increase of an inverse current from the base, and in that a spiking phenomenon may appear in which aluminum of the emitter electrode diffuses during sintering abnormally into the silicon substrate and the emitter is short-circuited to the base, thereby disabling to shallow the base-collector junction too much.
As a solution to the disadvantages of the first method, there has been proposed a method: in which one of main surfaces of a semiconductor substrate is covered with an insulating layer; a contact hole is opened on a definite position of the insulating layer; a polysilicon layer is deposited over the entire surface and impurities are diffused into the polysilicon layer; an interconnecting metal layer is further deposited onto the doped polysilicon layer; then the predetermined portion of the interconnecting metal layer is selectively removed; and the polysilicon layer is selectively removed using the selectively removed interconnecting metal layer as a mask. According to the above method, since the etching of the polysilicon layer is carried out by using the patterned interconnecting metal layer as a mask, and not by using a resist as a mask, the thinning of the polysilicon pattern can not occur. Moreover, with the same reason, the problem on the shear in alignment between the polysilicon and metal patterns can not occur. Also, since the doped polysilicon serves as a diffusion source, contact errors due to the shear in alignment between, for example, the polysilicon on the emitter and the base electrode can not occur, thereby enabling to make the edges of the emitter region and base region more closer in order to improve the high frequency performance.
The above proposed method, however, has many problems in forming both n.sup.+ and p.sup.+ regions in the silicon semiconductor substrate.
More in particular, in order to form both regions, first a resist pattern is formed which exposes a portion of the polysilicon layer under which a window portion is located, one of opposite conduction type regions being formed under the corresponding window portion. The impurities of the intended conductive type are injected into the exposed polysilicon layer, and the heating and diffusion processes are followed thereafter. Next, another resist pattern is formed which exposes a portion of the polysilicon layer under which a window portion is located, the other of opposite conduction type regions being formed under the corresponding window portion. The impurities of the intended conductive type opposite to that mentioned above are injected into the exposed polysilicon layer, and the heating and diffusion processes are followed. If n.sup.+ diffusion is first performed, the polysilicon layer injected with n type impurities such as phosphorus is twice subjected to thermal hysteresis including that in the following p.sup.+ diffusion. Thus, the diffusion area is broadened so that the base width in an npn transistor is narrowed to increase unnecessarily the current amplification ratio h.sub.FE, and it is almost impossible to control the ratio. Conversely, if p.sup.+ diffusion is first performed, the following disadvantages are brought about. For example, in order to improve the high frequency performance of a very high frequency transistor, it is necessary to have a shallow junction and a high dopant concentration base contact portion. For example, the depth of base junction is 0.3 .mu.m and the base surface concentration is in the order of 7.times.10.sup.18 atoms/cm.sup.2, and the p.sup.+ doping into the base contact portion is carried out at a high doping level in the order of 2.times.10.sup.20 atoms/cm.sup.2 at the surface concentration. In order to activate such high density doping region, for example, in the case of boron, a high temperature of 1000.degree. C. is required so that, if the emitter diffusion is carried out prior to the p.sup.+ region diffusion, the previously formed base junction is unnecessarily made deeper to thereby deteriorate the high frequency performance.
Further, the mobility of the p type impurities in the polysilicon layer reaches about 2.times.10.sup.-4 .mu.m.sup.2 /sec, wherein the polysilicon layer has a layer thickness of 4000 .ANG. and is formed by means of a low pressure chemical vapor deposition (LPCVD) method at a temperature of 625.degree. C. and under a growing speed of 100 .ANG./min, and wherein the doping level of boron is 2.times.10.sup.20 atoms/cm.sup.3 and the heating process is carried out at 1000.degree. C. The mobility of the p type impurities is larger than that of the n type impurities such as phosphorus and arsenic, respectively having in the order of 2.times.10.sup.-5 .mu.m.sup.2 /sec and 1.times.10.sup.-5 .mu.m.sup.2 /sec. Thus, in npn transistors, emitter diffusion about 10 minutes under 1000.degree. C. causes boron in the polysilicon to diffuse about 0.5 .mu.m, and annealing and diffusion of the p.sup.+ region under the like conditions prior to the emitter diffusion causes boron to move in total about 1 .mu.m. When the boron moves and reaches the polysilicon region ion-implanted with n.sup.+ impurities, boron ion first diffuses into the substrate and a leakage is likely to occur. That is, the inverse breakdown voltage between emitter and base is lowered due to high density boron ion, thus causing extreme disadvantages in the usage of transistors and changes of h.sub.FE.
In addition, the shorter the distance between windows formed in the insulating layer for forming emitter and base regions, the smaller the junction capacitance of the base. The high frequency performance can be expected to be improved with a smaller capacitance, and the distance can be shortened up to about 1 .mu.m in proportion to the improvement of the mask dimension accuracy. However, with the above method, such a minute configuration can not be obtained.